1. Field of the Invention
This invention relates to computer systems using cache memories, and especially to multiprocessing systems in which each processor has its own cache.
2. Discussion of Related art
A computer system would ideally use very fast memory for all of its temporary storage needs. This would allow the Central Processing Unit (CPU) to operate at its designed speed, without the need to wait for slower memory devices. However, slower memory is often used because it is less expensive, consumes less power, and provides more storage in a given space than does very fast memory.
A characteristic of most computer application programs is that they tend to perform repetitive operations on the same or neighboring pieces of data. Cache memory systems take advantage of this characteristic by storing recently accessed data in a small amount of very fast memory, called cache memory. Data which is read from slower main memory is stored in the faster cache memory, so that if a program must subsequently use the same data, it is available in cache memory. Thus, cache memory systems increase the apparent speed of memory accesses in computer systems.
A cache memory system must keep track of main memory addresses for which the associated data is available in the cache. When data is available in the cache, the data is directly provided to the CPU and the main memory is not accessed. This is called a cache "hit."
In a multiprocessor system, all CPUs may share a common main memory. In addition, each CPU may have its own cache memory. In the latter configuration, it is possible that data requested by one CPU is present in the cache of another CPU. Special circuitry is required to take advantage of this fact, i.e., to recognize a memory request from another CPU and then transfer the appropriate data directly between caches.
A special problem may occur when a CPU utilizes a "burst-mode" operation. Burst-mode operations are performed on data in a sequential series of memory locations. Rather than have the CPU execute a new instruction to address each individual memory location, burst-mode allows the CPU to execute a single instruction specifying a starting memory address, an operation to be performed, and the length of the memory block on which to perform the operation. This may cause particular problems in a multiple cache multiprocessor system when the starting memory address for a burst-mode operation starts in one cache and is completed in a different cache, or when all of the requested data is not present in a particular cache. In addition, burst-mode operations are subject to stringent timing requirements which dictate the use of specialized cache circuitry.